Embodiments of the present invention relate to a semiconductor memory device, and in particular, to a semiconductor memory device such as a dynamic random access memory (DRAM) having a temperature sensing circuit.
Various semiconductor devices, such as CPUs, memories, and gate arrays, implemented in integrated circuit chips are incorporated into various electrical products such as portable personal computers, PDAs, servers, workstations, etc. If such electrical products enter a sleep mode, most circuit components are turned off.
Semiconductor memory devices such as DRAMs are generally used as main memories for electrical systems and have unit memory cells each composed of one access transistor and one storage capacitor. Since semiconductor memory devices such as DRAM are volatile memories, in order to retain data stored in the memory cells, it is required to self-refresh data in the memory cells. Self refreshing results in power consumption. Demands for battery operated systems consuming a relatively smaller amount of power make it necessary to reduce power consumption.
One approach to reduce power consumption for self-refresh is to change a refresh interval in accordance with temperature. In DRAMs, as temperature becomes lower, a data retention period becomes longer. Accordingly, it is possible to divide a temperature range into two or more sub-ranges and decrease a frequency of a refresh clock with rising temperature, so as to reduce the power consumption. To this end, a low-power temperature sensing circuit is incorporated into a DRAM chip.
When a temperature sensing circuit is incorporated into a DRAM chip, a control circuit for calibrating the temperature sensing circuit, processing temperature-related data, and transmitting the processed data to a refresh circuit is incorporated as well. As the number of incorporated temperature sensing circuits and control circuits increases, more accurate temperature sensing and more precise refresh control become possible. However, it is difficult to incorporate a number of circuits without any restriction based on size.
For this reason, an improved technique for arranging circuits more effectively to reduce the occupied area of the circuits in a chip and perform precise refresh control is needed.